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Final Electrical Specifications
LTC1865L Power, 3V, 16-Bit, 150ksps 2-Channel ADC in MSOP
November 2002
FEATURES
s s s s
DESCRIPTIO
s s s
16-Bit 150ksps ADC in MSOP Package Single 3V Supply Low Supply Current: 450A (Typ) Auto Shutdown Reduces Supply Current to 10A at 1ksps SPI/MICROWIRETM Compatible Serial I/O 16-Bit Upgrade to 12-Bit LTC1288 Pin Compatible with 12-Bit LTC1861L
APPLICATIO S
s s s s
The LTC(R)1865L is a 16-bit A/D converter that is offered in MSOP and SO-8 packages and operates on a single 3V supply. At 150ksps, the supply current is only 450A. The supply current drops at lower speeds because the LTC1865L automatically powers down to a typical supply current of 1nA between conversions. This 16-bit switched capacitor successive approximation ADC includes a sample-and-hold. The LTC1865L offers a software-selectable 2-channel MUX. An adjustable reference pin is provided on the MSOP version. The 4-wire, serial I/O, MSOP or SO-8 package and extremely high sample rate-to-power ratio make this ADC an ideal choice for compact, low power, high speed systems. This ADC can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages.
High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency Single 3V Supply, 150ksps, 16-Bit Sampling ADC
1F 3V 1000 VCC = 2.7V TA = 25C CONV LOW = 2s
CH0 ANALOG INPUTS 0V TO 3V CH1
VREF CONV SCK LTC1865L SDO SDI AGND DGND
VCC
SUPPLY CURRENT (A)
100
10
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
1
1865L TA01
0.1 0.01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
U
U
0.1 10 100 1 SAMPLING FREQUENCY (kHz)
1000
1865 TA02
1865li
1
LTC1865L
ABSOLUTE
AXI U
RATI GS
Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND (MSOP Package) ....................... 0.3V Analog Input ............... (GND - 0.3V) to (VCC + 0.3V) Digital Input ................................ (GND - 0.3V) to 7V Digital Output .............. (GND - 0.3V) to (VCC + 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW CONV CH0 CH1 AGND DGND 1 2 3 4 5 10 9 8 7 6 VREF VCC SCK SDO SDI
ORDER PART NUMBER LTC1865LCMS LTC1865LIMS LTC1865LACMS LTC1865LAIMS MS PART MARKING LTJ4 LTJ5 LTJ6 LTJ7
CONV 1 CH0 2 CH1 3 GND 4
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JA = 210C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER A D
ULTIPLEXER CHARACTERISTICS
LTC1865L TYP MAX LTC1865LA TYP MAX
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V (MSOP) or VREF = VCC (SO), fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
PARAMETER Resolution No Missing Codes Resolution INL Transition Noise Gain Error Offset Error Analog Input Range Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance +CH - GND or (-CH) +CH Input -CH Input MSOP (Note 4) In Sample Mode During Conversion
q q q q
CONDITIONS
q q
(Note 3)
2
U
U
W
WW
U
WU
W
(Notes 1, 2)
Power Dissipation .............................................. 400mW Operating Temperature Range LTC1865LC ............................................ 0C to 70C LTC1865LI ........................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW 8 VCC 7 SCK 6 SDO 5 SDI
ORDER PART NUMBER LTC1865LCS8 LTC1865LIS8 LTC1865LACS8 LTC1865LAIS8 S8 PART MARKING 1865L 1865LI 1865LA 865LAI
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
U
MIN 16 14
MIN 16 15
UNITS Bits Bits
q
8 2 20 2 0 - 0.05 - 0.05 1 5 VREF VCC + 0.05 VCC /2 VCC 1 12 5 12 5 0 - 0.05 - 0.05 1 2 2
6 20 5 VREF VCC + 0.05 VCC /2 VCC 1
LSB LSBRMS mV mV V V V V A pF pF
1865li
LTC1865L
DY A IC ACCURACY
SYMBOL PARAMETER SNR THD Signal-to-Noise Ratio
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise noted.
CONDITIONS 1kHz Input Signal MIN TYP 82 82 92 10 S/(N + D) 75dB 20 MAX UNITS dB dB dB MHz kHz
S/(N + D) Signal-to-Noise Plus Distortion Ratio Full Power Bandwidth Full Linear Bandwidth
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PD High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (MSOP) Supply Current Power Dissipation CONDITION VCC = 3.3V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10A VCC = 2.7V, IO = 360A VCC = 2.7V, IO = 400A CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V (MSOP) or VREF = VCC (SO), unless otherwise noted.
MIN
q q q q q q q q
RECO
VCC fSCK tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV
full operating temperature range, otherwise specifications are TA = 25C.
CONDITIONS Supply Voltage Clock Frequency Total Cycle Time Analog Input Sampling Time Setup Time CONV Before First SCK (See Figure 1) Hold Time SDI After SCK Setup Time SDI Stable Before SCK SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK fSCK = fSCK(MAX) fSCK = fSCK(MAX)
E DED OPERATI G CO DITIO S
SYMBOL PARAMETER
U
U
U
U WW
U
WU
Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal
TYP
MAX 0.45 2.5 - 2.5
UNITS V V A A V V
1.9
2.3 2.1
2.60 2.45 0.3 3 - 6.5 6.5
V A mA mA
q q q q
0.001 0.01 0.5 0.45 1.22
3 0.1 10 1
A mA A mA mW
The q denotes specifications which apply over the
MIN 2.7
q
TYP
MAX 3.6 8
UNITS V MHz s SCK ns ns ns 1/fSCK 1/fSCK s SCK ns
1865li
DC 16 * SCK + tCONV 14 60 30 30 45% 45% tCONV 16 26
3
LTC1865L
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 2.7V, VREF = 2.5V (MSOP) or VREF = VCC (SO), fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL tCONV tdDO tdis ten thDO tr PARAMETER Conversion Time (See Figure 1) Delay Time, SCK to SDO Data Valid Delay Time, CONV to SDO Hi-Z Delay Time, CONV to SDO Enabled Time Output Data Remains Valid After SCK SDO Rise Time CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF
q q q q
TI I G CHARACTERISTICS
fSMPL(MAX) Maximum Sampling Frequency
tf SDO Fall Time CLOAD = 20pF Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND.
4
UW
CONDITIONS
q q
MIN 150
TYP 3.7 45 55 35
MAX 4.66 55 60 120 120
UNITS s kHz ns ns ns ns ns ns
5
15 25
12 ns Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Channel leakage current is measured while the part is in sample mode.
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LTC1865L TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling Frequency
1000 VCC = 2.7V TA = 25C CONV LOW = 2s
SUPPLY CURRENT (A)
100
INL ERROR (LSBs)
10
0
DNL ERROR (LSBs)
1
0.1 0.01
0.1 10 100 1 SAMPLING FREQUENCY (kHz)
4096 Point FFT Nonaveraged
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0
VCC = 3V VREF = 3V fS = 125kHz fIN = 1kHz
AMPLITUDE (dB)
SINAD (dB)
50 40 30 20 10 0
SNR (dB)
5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT FREQUENCY (kHz)
1865 G04
THD vs Input Frequency
0 -10 -20 -30 SFDR (dB) THD (dB) - 40 -50 -60 -70 -80 -90 -100 1 10 fIN (kHz) 100
1865 G07
VCC = 3V VREF 3V fS = 125kHz
UW
1865 TA02
Typical INL Curve
4 VCC = 2.7V VREF = 2.5V 2
2
Typical DNL Curve
VCC = 2.7V VREF = 2.5V
1
0
-2
-1
-4 1000
0
16384
32768 CODE
49152
65536
1865 G02
-2
0
16384
32768 CODE
49152
65536
1865 G03
SINAD vs Input Frequency
100 90 80 70 60 VCC = 3V VREF 3V fS = 125kHz 100 90 80 70 60 50 40 30 20 10 1 10 fIN (kHz) 100
1865 G05
SNR vs Input Frequency
VCC = 3V VREF 3V fS = 125kHz 1 10 fIN (kHz) 100
1865 G06
0
SFDR vs Input Frequency
100 90 80 70 60 50 40 30 20 10 0 1 10 fIN (kHz) 100
1865 G08
VCC = 3V VREF 3V fS = 125kHz
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5
LTC1865L
PI FU CTIO S
(MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin.
BLOCK DIAGRA
6
W
U
U
U
VCC
CONV SDI
SCK
CONVERT CLK
BIAS AND SHUTDOWN DATA IN
SERIAL PORT
SDO
16-BITS CH0 CH1
+ -
16-BIT SAMPLING ADC
DATA OUT
1865 BD
GND
VREF (MSOP ONLY)
1865li
LTC1865L
TEST CIRCUITS
Load Circuit for t dDO, tr, t f, tdis and t en
TEST POINT
Voltage Waveforms for SDO Rise and Fall Times, tr, t f
SDO VOH VOL
3k SDO 20pF
VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1
1864 TC01
tr
tf
1864 TC04
Voltage Waveforms for t en
CONV
Voltage Waveforms for t dis
CONV
SDO ten
1864 TC03
VIH
SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2)
90%
Voltage Waveforms for SDO Delay Time, t dDO and t hDO
SCK VIL tdDO thDO VOH SDO VOL
1864 TC02
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1864 TC05
1865li
7
LTC1865L
APPLICATIO S I FOR ATIO
Operating Sequence
The LTC1865L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1865L goes into sleep mode. If CONV goes low before the conversion is finished, it will terminate the conversion and the output data will be invalid. To prepare for the next conversion, it is still necessary to clock in the new data input word and shift out the invalid data output word. The next conversion cycle can then proceed normally. The LTC1865L's 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of Table 1. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the "+" input minus the "-" input equals zero. Full scale occurs when the "+" input minus the "-" input equals V REF minus
CONV tCONV SLEEP MODE
SDI
DON'T CARE
SCK
SDO
Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Figure 1. LTC1865L Operating Sequence
1865li
8
U
1LSB. See Figure 2. Both the "+" and "-" inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the "-" input in differential mode is grounded, a rail-to-rail input span will result on the "+" input. Reference Input The reference input of the LTC1865L SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1865L MSOP package defines the span of the A/D converter. The LTC1865L MSOP package can operate with voltages from 1V to VCC.
Table 1. Multiplexer Channel Selection
MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + - - + GND - - SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE
1864 TBL1
W
UU
GENERAL ANALOG CONSIDERATIONS Grounding The LTC1865L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the MSOP package and GND for the SO-8 package) should be
t SMPL
S/D O/S 1 2 3 4 5 6 7
DON'T CARE 8 9 10 11 12 13 14 15 16
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
1865L F01
LTC1865L
APPLICATIO S I FOR ATIO
tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1F tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1865L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source
U
resistances are less than 200 or high speed op amps are used (e.g., the LT(R)1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins.
1111111111111111 1111111111111110
W
UU
* * *
0000000000000001 0000000000000000 VIN*
Figure 2. LTC1865L Transfer Curve
0V
*VIN = (SELECTED "+" CHANNEL) - (SELECTED "-" CHANNEL) REFER TO TABLE 1
1LSB
VCC
VCC - 1LSB
VCC - 2LSB
1864 F02
1865li
9
LTC1865L
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.13 0.076 (.005 .003)
MSOP (MS) 0802
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
10
U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.2 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.01 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.86 (.034) REF 4.90 0.15 (1.93 .006) 3.00 0.102 (.118 .004) NOTE 4 0.50 (.0197) BSC
1865li
LTC1865L
PACKAGE DESCRIPTIO U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 .005 .050 BSC 8 N N .245 MIN .160 .005 .228 - .244 (5.791 - 6.197) 1 .030 .005 TYP 2 3 N/2 N/2 .150 - .157 (3.810 - 3.988) NOTE 3 .189 - .197 (4.801 - 5.004) NOTE 3 7 6 5 1 2 3 4 .053 - .069 (1.346 - 1.752) 0- 8 TYP .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
SO8 0502
RECOMMENDED SOLDER PAD LAYOUT
.010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254)
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
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LTC1865L RELATED PARTS
PART NUMBER 8-Bit Serial I/O ADCs LTC1096/LTC1096L LTC1098/LTC1098L LTC1196 LTC1198 10-Bit Serial I/O ADCs LTC1197/LTC1197L LTC1199/LTC1199L 12-Bit Serial I/O ADCs LTC1286/LTC1298 LTC1400 LTC1401 LTC1402 LTC1404 LTC1860/LTC1861 LTC1860L/LTC1861L 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 LTC1864/LTC1865 LTC1864L 200ksps 250ksps 150ksps 65mW 4.25mW 1.22mW Configurable Bipolar or Unipolar Input Ranges, 5V SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V SO-8, MS8, 1-Channel, 3V 400ksps 200ksps 20mW 15mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V Serial/Parallel I/O, Internal Reference, 5V 12.5ksps/11.1ksps 400ksps 200ksps 2.2Msps 600ksps 250ksps 150ksps 1.3mW/1.7mW 75mW 15mW 90mW 25mW 4.25mW 1.95mW 1-Channel with Reference (LTC1286), 2-Channel (LTC1298), 5V 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V SO-8 with Reference, 3V Serial I/O, Bipolar or Unipolar, Internal Reference SO-8 with Reference, Bipolar or Unipolar, 5V SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V SO-8, MS8, 1-Channel, 3V/SO-8, MS10, 2-Channel, 3V 500ksps/250ksps 450ksps/210ksps 22.5mW 25mW SO-8, MS8, 1-Channel, 5V/3V SO-8, MS8, 2-Channel, 5V/3V 15ksps 15ksps 1Msps 750ksps 0.9mW 0.6mW 20mW 20mW 1-Channel, Unipolar Operation, 5V/3V 2-Channel, Unipolar Operation, 5V/3V 1-Channel, Unipolar Operation with Reference Input, 5V/3V 2-Channel, Unipolar Operation, 5V/3V SAMPLE RATE POWER DISSIPATION DESCRIPTION
PART NUMBER References LT1460 LT1790 Op Amps LT1468/LT1469 LT1806/LT1807 LT1809/LT1810
DESCRIPTION Micropower Precision Series Reference Micropower Low Dropout Reference Single/Dual 90MHz, 16-Bit Accurate Op Amps Single/Dual 325MHz Low Noise Op Amps Single/Dual 180MHz Low Distortion Op Amps
COMMENTS Bandgap, 130A Supply Current, 10ppm/C, Available in SOT-23 60A Supply Current, 10ppm/C, SOT-23 22V/s Slew Rate, 75V/125V Offset 140V/s Slew Rate, 3.5nV/Hz Noise, - 80dBc Distortion 350V/s Slew Rate, - 90dBc Distortion at 5MHz
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12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 1102 1.5K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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